The present invention relates generally to programming arrangements for matrices and, more particularly, to programming arrangements which involve application of programming and/or programming control signals to output terminals as a part of the programming operation.
Programmable memory devices, such as RAMS, PROMS, EPROMS, EEPROMS, etc., are typically programmed by techniques which include addressing of a desired memory location and application of a programming signal, or a programming control signal, to an output terminal which corresponds to the addressed location. This latter step is often accompanied by the application of one or more PROGRAM mode enable signals to selected device terminals. Due to the relative shortage of available pins on most memory devices, the enable signals and/or the signals applied to the output terminals are often relatively high level (i.e., supervoltage) signals, allowing individual pins to be used for more than one function.
U.S. Pat. No. 4,125,880 to Taylor is a Harris Corporation Patent which illustrates a programming technique of this type. In Taylor, a ten volt signal is applied to output pin 60, causing a zener diode 74 to conduct and transistor 72 to turn on. The power supply terminal V.sub.CC, which is connected to the collectors of the transistors in the matrix, is raised from the normal operating level of 5 volts to a programming level of 12 volts. When a selected memory location is addressed, diode 78 and transistor 72 provide a low impedance current sink for the flow of programming current resulting from the high collector voltage present at the selected memory location. A voltage is applied to chip enable terminal 20 to turn off transistor 52 to prevent programming currents or voltages from damaging output transistor 58.
Although the use of "zenered" or supervoltage inputs does expand the range of programming and testing functions which can be implemented on a given device, this technique does not entirely alleviate the pin shortage problem. Furthermore, increased use of higher than normal logic level voltages for programming or control functions can result in increased power consumption and can require additional circuitry to provide protection for voltage sensitive components. Accordingly, there exists a need for a programming arrangement which allows for expanded use of the available device pins, and for simplified programming of additional features and special matrix functions associated with particular devices, without requiring an increase in the use of supervoltage programming techniques.
The present invention relates to a programming arrangement for programmable matrices of the above-noted types which provides a means for controlling the flow of programming current to any of the individual memory locations in the matrix by application of programming signals to less than all of the device output terminals. The remaining output terminals are thus available for use in programming and/or selection of a variety of special matrix functions which may be advantageously incorporated into particular devices.
As used in this application, the term "special matrix function" is intended to include all selectable or controllable features associated with a device, over and above the "normal" addressing and programming of the individual memory locations. For example, a special matrix function can include the provision of a programmable output polarity feature. Such a feature could be activated to invert selected outputs when a coded command is given via the "extra" output terminals available on a device constructed according to the present invention. Another example (discussed in more detail below) involves the programming of redundant rows and/or columns in a matrix. Yet another example is use of one or more of the available outputs to control a selectively synchronous or asynchronous chip enable function. In this example, the outputs of a device can be selectively tri-stated (i.e., allowed to float) in response to a clock pulse (the synchronous mode) or upon command (the asynchronous mode) by programming signals applied to output terminals made available by the programming arrangement of the present invention.
Accordingly, an object of this invention is to provide a programming arrangement for a matrix which allows for programming of desired memory locations and an increased number of special matrix functions using presently available input and output terminals.
Another object of the present invention is to provide a programmable matrix with expanded programming capabilities which does not require the use of additional supervoltage input terminals.
These objects are attained in a programmable matrix which comprises a plurality of memory elements arranged in an array of X by Y intersecting lines, inputs for addressing at least a portion of the Y lines, and input/output apparatus for receiving a sensing signal from an addressed memory element when the matrix is operating in a sense mode and for addressing the X lines of the matrix when the matrix is operating in a programming mode. The input/output apparatus includes N input/output terminals and programming apparatus for controlling a flow of programming current to any of the memory elements by application of programming signals to less than all of the N terminals. The programming apparatus includes a programming decoder having a first set of outputs for controlling the flow of programming current to the matrix in response to programming signals present at the decoder inputs which are connected to a subset of the N terminals. The decoder also includes a second set of outputs for addressing special matrix functions (such as redundant columns or rows, programmable output polarity states, etc.) in response to programming signals applied to at least one of the N terminals. In a preferred embodiment, the number of input/output terminals N is equal to 8. In this embodiment, the X lines of the matrix are addressed by application of programming signals to three of the eight input/output terminals. A fourth terminal is used to accept a strobe signal to initiate a programming operation. The remaining four terminals are used as inputs for addressing other functions. If used independently of the three outputs used for programming the matrix, 16 additional functions may be addressed. If combined with the three terminals used for matrix programming, a total of 120 additional functions can be addressed. In alternative embodiments, N may be equal to four or sixteen.
Using this technique, a memory element to be programmed is addressed by the Y line inputs and by a subset of the N input/output terminals. A programming strobe signal is applied to one of the remaining input/output terminals and a flow of programming current is triggered. To program a special function, the "address" applied to the input/output terminals is changed and the strobe initiated to effect the desired programming. This technique results in expanded programmability of the matrix, while eliminating the need for additional supervoltage pins.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.